The present invention relates generally to the fabrication of silicon gate structures and more specifically to improvements in fabricating a narrow gate structure on a high-K dielectric, for a high density gate array on a silicon integrated circuit.
Many silicon devices used in modern integrated circuits utilize a field effect transistor structure that comprises a polysilicon gate positioned over a channel region within a silicon wafer. For example, a typical field effect transistor cell comprises such a structure with a insulating layer separating the polysilicon gate from the channel region. As another example, a typical floating gate flash memory cell includes additional layers between the polysilicon gate and the channel region that comprise a tunnel oxide layer, a floating gate layer, and an oxide-nitride-oxide (ONO) layer. In addition to these examples, cell structures for read only memory (ROM), random access memory (RAM), SONOS type flash memory, and other planar silicon integrated circuit structures all utilize a polysilicon gate positioned over a channel region.
The typical process for fabricating a polysilicon gate is to first grow an oxide on the surface of a wafer followed by applying a polysilicon layer. An anti-reflective coating and a photoresist layer are then deposited over the polysilicon layer, patterned, and developed to mask the polysilicon gate. An anisotropic etch is then used to remove the un-masked polysilicon such that the polysilicon gate is formed.
It is a generally recognized goal to decrease the size of the polysilicon gate. First, decreasing the gate size permits decreasing the size of each individual silicon device. Decreasing the size of each devices provides the ability to increase the density of a device array fabricated on a wafer which, provides the ability to fabricate a more complex circuit with a faster operating speed on a wafer of a given size. Secondly, a smaller channel region beneath a smaller gate reduces capacitance across the channel/source junction and the channel drain junction which provides for faster operating speed and reduced power consumption.
One problem with reducing the gate size is that these exists a minimum physical thickness of the gate oxide at which the oxide no longer isolates the gate from the channel region. Because smaller gate sizes require better capacitive coupling between the gate and the channel region and because the gate oxide can not be scaled below the minimum thickness, other dielectrics with dielectric constants greater than silicon dioxide (e.g high K dielectrics) may be used to replace the conventional gate oxide to improve capacitive coupling. However, high K dielectrics react to various etching chemistries differently than silicon dioxide and therefore the use of a high K gate dielectric requires different fabrication methods than a similar structure with a conventional gate oxide.
Another problem with reducing gate size is that limitations on the masking and etching processes limit gate size. For example, the resolution of the photoresist masking processes provides a limit on the minimum gate size and etching processes for etching vertical surfaces perpendicular to the horizontal mask further limit the minimum gate size due to erosion and other effects that degrade the etch profile.
Accordingly there is a strong need in the art for a method of fabricating a narrow polysilicon gate that provides for reduced gate size and improved side wall tolerance. There is also a strong need in the art for such method to provide for improved capacitive coupling and improved isolation between the channel region and the gate to support a narrower polysilicon gate.
A first aspect of the present invention is to provide an efficient method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etching, and the removal or exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. Such method of performing in-situ resist trim, gate etch, and high-K gate dielectric removal provides for a simplified process over known fabrication methods along with improving throughput. The method also reduces wafer handling and opportunities for contamination. The method comprises fabricating a gate dielectric etch stop layer above a polysilicon substrate. The gate dielectric etch stop layer comprising a material that has a dielectric constant greater than the dielectric constant of silicon dioxide and forms the gate dielectric in a region of the wafer that becomes the gate and forms a barrier to prevent polysilicon etching chemistries from damaging the polysilicon silicon substrate in regions along side the gate. The method further comprises sequentially: a) fabricating a polysilicon layer above the gate dielectric etch stop layer; b) fabricating a bottom anti reflective coating (BARC) above the polysilicon layer; and c) fabricating a photoresist layer over the BARC. The photoresist layer is then patterned and developed to form a mask over a gate region and to expose an erosion region about the periphery of the gate region.
The wafer is placed in an enclosed etching environment with a high density plasma and, optionally an inert gas. The inert gas may be argon. While in such an etching environment the following etch processes are in-situ performed: a) a portion of the mask is etched to form a trimmed mask over a narrow gate region and to increase the size of the erosion region using an etch chemistry selective between the photoresist and the anti reflective coating, the trimmed mask dimension is beyond the capability of either 248 nm or 193 nm lithography; b) the anti reflective coating is etched within the erosion region; c) the polysilicon layer is etched using an etch chemistry selective between the polysilicon and each of the trimmed mask and the gate dielectric etch stop layer; and d) the gate dielectric etch stop layer is removed using an etch chemistry selective between the gate dielectric etch stop layer and polysilicon.
The gate dielectric etch stop layer may comprise a high K material selected from the group of HfO2, ZrO2, CeO2, Al2O3, TiO2, Y2O3. Within the environment, the step of trimming or etching a portion of the mask may comprise use of at least one of HBr, CL2, N2, He and O2 and the step of etching the anti reflective coating may comprises use of CF4 or CHF3. The step of etching the polysilicon layer may comprise use of HBr, Cl2, CF4, and HeO2 (a combination of Oxygen diluted with a large amount of Helium provided to the etch chamber through a single mass flow controller), in a bias field to improve a vertical side profile between the gate region and the erosion region of the polysilicon. The HeO2 increases the selectivity between the polysilicon and the gate dielectric etch stop layer. Other etch parameters may also be used to improve the selectivity between the polysilicon and the gate dielectric etch stop layer. The step of removing the gate dielectric etch stop layer comprises use of HBr and, He with the addition of fluorine gas.
A second aspect of the present invention is to provide a similar method for fabricating a non volatile memory device on the surface of a polysilicon wafer utilizing in-situ resist trim, control gate etch, interpoly dielectric etch, polysilicon etch, and tunnel dielectric removal. The method comprises fabricating a tunnel dielectric etch stop layer above a polysilicon substrate. The tunnel dielectric etch stop layer comprises a material that has a dielectric constant greater than the dielectric constant of silicon dioxide and forms the tunnel dielectric in a region of the wafer that becomes the memory cell and forms a barrier to prevent polysilicon etching chemistries from damaging the polysilicon silicon substrate in regions along side the memory cell. The method further comprises sequentially: a) fabricating a polysilicon layer above the tunnel dielectric etch stop layer; b) fabricating an interpoly dielectric layer above the polysilicon layer; c) fabricating a polysilicon control gate layer above the interpoly dielectric layer; d) fabricating an anti reflective coating above the polysilicon layer; and e) fabricating a photoresist layer over the anti reflective coating layer. The photoresist layer is then patterned and developed to form a mask over a memory cell region and to expose an erosion region about the periphery of the memory cell region.
The wafer is placed in an enclosed etching environment with a high density plasma and, optionally an inert gas. The inert gas may be argon. While in such an etching environment the following etch processes are performed in-situ. First, a portion of the mask is etched to form a trimmed mask over a narrow memory cell region and to increase the size of the erosion region using an etch chemistry selective between the photoresist and the anti reflective coating. The trimmed mask has a mask dimension smaller than the capability of the lithography process (248 nm or 193 nm). Secondly, the anti reflective coating is etched within the erosion region. Thirdly, the polysilicon gate is etched using an etch chemistry selective between the polysilicon and the trimmed mask. Fourthly, the interpoly dielectric layer is etched using an etch chemistry selective between the interpoly dielectric and the trimmed mask. Fifthly, the polysilicon layer is etched using an etch chemistry selective between the polysilicon and each of the trimmed mask and the tunnel dielectric etch stop layer. And, sixthly, the tunnel dielectric etch stop layer is removed using an etch chemistry selective between the tunnel dielectric etch stop layer and polysilicon.
The tunnel dielectric etch stop layer may comprise a high K material selected from the group of HfO2, ZrO2, CeO2, Al2O3, TiO2, Y2O3. The inert gas may be argon. Within the environment, the step of trimming or etching a portion of the mask may comprise use of at least one of HBr, CL2, N2, He and O2 and the step of etching the anti reflective coating may comprises use of CF4 or CHF3. The step of etching each of the polysilicon gate dielectric layer and the interpoly dielectric layer may comprise the use of HBr, Cl2, CF4, and HeO2, in a bias field to improve a vertical side profile between the gate region and the erosion region. Further, etching the polysilicon layer may comprise use of HBr, Cl2, CF4, and HeO2 in combination with HeO2 to increase the selectivity between the polysilicon and the tunnel dielectric etch stop layer. Other etch parameters may also be used to improve the selectivity between the polysilicon and the tunnel dielectric etch stop layer. The step of etching the tunnel dielectric etch stop layer comprises use of HBr and, He with the addition of fluorine gas.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.